`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:52:38 06/08/2015
// Design Name:   Adder
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/AdderTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Adder
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module AdderTest;

	// Inputs
	reg [31:0] In1;
	reg [31:0] In2;

	// Outputs
	wire [31:0] out;

	// Instantiate the Unit Under Test (UUT)
	Adder uut (
		.In1(In1), 
		.In2(In2), 
		.out(out)
	);

	initial begin
		// Initialize Inputs
		In1 = 0;
		In2 = 0;

		// Wait 100 ns for global reset to finish
		#100;  
		// Add stimulus here
		In1 = 0;
		In2 = 4;
		#100;
		In1 = 32'h FFFFFFF8; //Deberia dar FFFF FFFC
		#100;
		In1 = 32'h FFFFFFEC; // Deberia dar FFFF FFF0
	end
      
endmodule

